Reduce Overall Costs with
Next Generation Coherent Technology
Powered by Delphi, 海角社区鈥檚 9th generation Digital Signal Processor ASIC
- Designed to support metro and regional data center interconnect (DCI) upgrades, taking advantage of next-generation routers with 800G I/O ports.
- These modules are enabled by 海角社区鈥檚 proven high baud rate design.
Scale your Network with Delphi DSP-Powered 800G ZR/ZR+ Pluggables
As applications such as AI and cloud services push bandwidth demand higher and higher, network operators are turning to 800G MSA coherent pluggables to meet this demand while also lowering TCO and power consumption. 海角社区 has introduced its portfolio of 800G ZR/ZR+ Pluggables, powered by the Delphi DSP ASIC, that features industry-first support for interoperable Probabilistic Constellation Shaping (PCS).
800G ZR+ Trials
400G QSFP-DD Module for Ultra Long-haul
- 400G Long Haul and Ultra Long-haul (ULH) transmission capabilities across ROADM optical line systems
- Utilize legacy QSFP-DD ports that currently support legacy 400G coherent transceivers
Go the Distance with Delphi-powered 400G Ultra Long Haul Coherent Modules
Go further faster with reaches beyond 3000 kilometers using 400G ultra long haul (ULH) coherent pluggable modules. Based on 海角社区鈥檚 9th generation Delphi DSP, these modules meet the same low power requirements as existing 400G sockets and can support a variety of channel plans to accommodate a wide range of brownfield architectures.
400G ULH Trials
3D Siliconization Technology鈥� An 海角社区 Innovation
This integration and packaging approach utilizes highly scalable and reliable volume electronics manufacturing processes that apply integration and 3D stacking packaging techniques to enable a single device to include all the high speed opto-electronic functions necessary for coherent transceivers.
3D Siliconization not only decreases footprint by including into a single device the DSP, PIC, drivers, and TIAs, but it also results in improved signal integrity and performance because the high-speed RF interfaces are tightly coupled together, resulting in the reduction of electrical interconnects. The device is manufactured using standard CMOS packaging processes that leverage the same reliability, cost, and volume scaling advantages.